2011/asyn11

Neuromorphic Asynchronous Circuits

Members: Ashley Liddiard, Brian Mingus, Daniel B. Fasnacht, Emmett McQuinn, Fabio Stefanini, Francisco Barranco, Francesco Galluppi, Gert Cauwenberghs, John Harris, Je Hi An, Jonathan Tapson, Jayawan Wijekoon, Roi Kliper, Kwabena Boahen, Katie Zhuang, Peiran Gao, Dr. Hasler, Rajit Manohar, Ryad Benjamin Benosman, Ravi Shekhar, Runchun Wang, saber moradi, Samantha Adams, Sergio Davies, Shih-Chii Liu, Siddharth Joshi, Trevor Agus, Timir Datta, Tomas Figliolia, Timmer Horiuchi, Tobi Delbruck, Terry Stewart, Yan Wu

Leaders: Rajit Manohar (Cornell), Shih-Chii Liu (UZH and ETH Zurich)

Shih-Chii Liu shih@… 26-Jun 16-Jul
Rajit Manohar rajit@… 26-Jun 16-Jul (absent Jul 2-4)

Participate in this directors' invited tutorial workgroup to learn how to implement neuromorphic VLSI systems with asynchronous digital circuits. We will also provide a tutorial introduction to asynchronous design using state-of-the-art tools for designing asynchronous circuits.

Both topic leaders have experience with fabricating real asynchronous designs; Rajit Manohar is a founder of a  Achronix, the first suppliers of asynchronous FPGAs.

Summary of Results

A total of eight sessions were organized as part of this tutorial, seven of them being tutorial in nature and the eighth being a discussion of various approaches to large-scale neuromorphic systems.

Tutorials

  • Session 1: A general overview of asynchronous design, and its applicability to neural systems.
  • Session 2: Hands-on installation of tools for the FPGA-based BASYS2 rapid prototyping platform.
  • Session 3: Dataflow computation as a means to rapidly design asynchronous circuits.
  • Session 4: Converting CHP programs to handshaking expansions and production rules.
  • Session 5: Bubble reshuffling, circuit issues with staticizer design.
  • Session 6: Standard circuit templates
  • Session 7: Using prs2v to create a prototype of an asynchronous circuit using synchronous FPGAs. This tool was developed during the workshop.

The tutorial concluded with a live demonstration of a simple asynchronous circuit implemented using standard dataflow blocks mapped to the BASYS2 board, with the output being displayed using a USB scope showing correct operation, as illustrated on the scope trace below. The traces show alternating zeros and ones being produced by the alt machine.

alternating bits out of basys2 from alt machine

Detailed materials used during the tutorial are below.

Tutorial Material

  •  Paper on a systematic method to convert programs into static dataflow graphs.
  • See attachment:asynDiscussion772011.pdf Download for notes from the morning discussion on asynchronous computation and communication - 5 minute presentations from 6 people, ranging up to large scale neural hardware systems.

Background

Numerous neuromorphic engineering researchers have to struggle with the design of complex asynchronous circuits, even though this is not the focus of their research activity. The lack of commercially available design automation tools for asynchronous logic exacerbates this problem. The goal of this topic area is to create asynchronous designs of the key components of neuromorphic systems, as well as understand the different design options and trade-offs. The topic area will contain a hands-on introduction and tutorial on the systematic design of asynchronous circuits, supported by tools to simulate these circuits at different levels of abstraction.

Asynchronous design methodologies make it possible to create robust circuits where the key elements of the circuit are technology-independent. One of the benefits of these circuits is that they are highly modular, and components can be re-used across different designs and across technology generations. Our goal in this topic area is to create and maintain a repository of parametrized components required to implement the main digital elements of any neuromorphic architecture.

The first week will focus on a practical introduction to asynchronous design. Lectures on asynchronous design will be interleaved with the use of tools that can be used to describe asynchronous circuits and simulate them at different levels of abstraction. At the highest level, systems will be described using the communicating hardware processes (CHP) notation. At the most detailed level, production rule sets (PRS) provide a notation for a compact circuit netlist description. The week will focus on converting a high-level description of a neuromorphic system into production rules, with an emphasis being placed on examples drawn from the neuromorphic community.

All files will be designed using the ACT language for asynchronous design. This language enables a parametrized description of complex asynchronous systems at multiple levels of abstraction. The language is a successor to various design entry languages developed at Caltech, and has been created by the Cornell asynchronous VLSI group. The language has been used to design multiple complex asynchronous systems including complete microprocessors, floating-point hardware, and asynchronous FPGAs. Participants will be able to use a complete design flow for the creation of neuromorphic systems from a high-level description.

Different designs created over the three weeks will be made available to the neuromorphic design community via a web-based repository. We plan to maintain this repository in future years, so that researchers can share their designs with each other. This will also provide a basis for comparing new architectures and circuit designs against each other, since reference designs will be readily available to the community.

Possible Topic Area Projects

The overall goal is to create a repository of asynchronous designs and architectures suitable for neuromorphic engineers. These will be made available on the web for community use.

Neuromorphic components

  • Design an AER system. Goal: to create a production-rule implementation of an AER system suitable for 1-D and 2-D organizations. Ravi Shekhar
  • Design an AER router. Goal: to create a production-rule implementation of an address-event router.
  • Design a lookup table. Goal: to create circuits for a memory structure suitable for route lookups. Participants: Shih-Chii Liu, Peiran Gao
  • Design a jAER visual filter. Goal: to create circuits for implementing a jAER orientation filter. Participants: Shih-Chii Liu, Ravi Shekhar

Routing architecture

Goal: to compare a variety of routing architectures for suitability (throughput, latency, area) in the implementation of large-scale neuromorphic systems using a combination of analysis and simulation.

Neuromorphic prototyping platform

Goal: to create a method for fast prototyping of asynchronous circuits by converting them to ”synchronized” versions and prototyping them on commercially available FPGAs. We will use  Digilent BASYS2 boards with Xilinx Spartan 3E FPGAs for this part. See  this page for tool setup if you want to install the FPGA tools yourself, or see below if you want a pre-installed virtual machine environment that you can also use to run the async ACT design tools.

Ubuntu virtual machine setup for FPGA prototyping

You will need a linux machine to run the async tools. For convenience, you can run the FPGA development tools from Xilinx inside an Ubuntu linux virtual machine so that we can run the async tools on the same machine.

To set this up follow these steps: You will need 15GB of free disk space.

  1. In order to get started the best way is that you install the latest version of VirtualBox? from  http://virtualbox.org for your OS.
  2. Connect to the LAN (wired) not Wireless-LAN. Switches to connect to are on the big table groups, extra cables are in a box next to the printer.
  3. Download the .OVA file from:

 http://soggy.neuromorphs.net/mirror/asyn/

  1. Start VirtualBox, and import the file through File -> Import Appliance...
  • Login: vfpga
  • Password: changeme

To see a Windows folder in vfpga VM do this:

  1. In VirtualBox highlight the Virtual Machine (vfpga) and click on 'Settings'
  2. In the left-hand panel click on 'Shared Folders'
  3. Click on the Add shared folder icon (on the right it is an icon of a folder with a +)
  4. Click on arrow on Folder Path box and click 'Other'
  5. Browse to required directory, click OK
  6. Select 'Auto Mount' option
  7. Click OK

After launching vfpga VM the shared drive is viewable under /media directory

Xilinx ISE

In order to run the Xilinx ISE open a terminal (icon in the panel) and execute runise

Adept utilties for programming BASYS2 boards from Linux

Adept is started with the cryptic djtgcfg

If you don't have Adpet installed, you can install yourself. Install the following:

  1. Adept runtime from attachment:digilent.adept.runtime_2.8.2-i686.tar.gz Download
  2. Adept Utilities from attachment:digilent.adept.utilities_2.1.1-i686.tar.gz Download

You can also get these from  http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2

To install, expand the archive, open a terminal, then cd to the folder and do 

sudo ./install.sh

The sudo password is the same as your login.

The VM is set up to map your BASYS2 board through the USB bus to the VM. You might need to select the device from the VirtualBox Devices menu. The

Notes

Because the Floorplaner didn't start, I had to add to the “settings.sh” at toplevel if ISE directory: 

export DISPLAY=:0

More possible problems discussed at  https://help.ubuntu.com/community/XilinxISE

Adept starts with the command: djtgcfg.

To enumerate your devices 

djtgcfg enum

Here is an example run: 

vfpga@vfpga:~/Documents/asyn/digilent.adept.utilities_2.1.1-i686$ djtgcfg enum
Found 1 device(s)

Device: Basys2
    Product Name:   Digilent Basys2-250
    User Name:      Basys2
    Serial Number:  210155261936

To program your board 

  djtgcfg prog -d Basys2 -i 1 -f design.bit

-i 1 to select the PROM if the jumper is set to ROM; design.bit is your bit file.

Here is an example run: 

vfpga@vfpga:~/Documents/asyn/SnakeGameJeffreyGehrig$ djtgcfg prog -d Basys2 -i 1 -f Snake.bit
Erasing PROM. Do not touch your board. This may take a few minutes...
Erase succeeded.
Programming device. Do not touch your board. This may take a few minutes...
Programming succeeded.
vfpga@vfpga:~/Documents/asyn/SnakeGameJeffreyGehrig$

Access restricted. Please log in.

Attachments